1. Description

The I2C-HAT communication protocol is a request/response type protocol, Raspberry Pi issues a request frame an gets a response frame back from the I2C-HAT, usually this takes about 2ms, depends on what was the I2C-HAT was requested to do. The frame data integrity is ensured by a 16bit CRC(same as Modbus).

The I2C bus master(Raspberry Pi) will use a I2C write operation to send a request to the I2C-HAT. To get the response back from the I2C-HAT the I2C bus master must use a I2C read operation. Both I2C read and I2C write operations should be targeted to the I2C bus address of the I2C-HAT. Payload data of the I2C read and I2C write operations is packed in frames.

Te I2C-HAT will use clock-stretching until processing the request from the master has finished, so if master wants to read the response while I2C-HAT is still processing the request the read will get clock-stretched.

2. I2C Frame

Field Name Size(bytes) Description
Id 1 Frame identification
Command 1 Command to be executed by the I2C-HAT
Data n Payload data, data size(n) is determined by the Command
Crc 2 Modbus 16 bit CRC

I2C frame implementations:

  1. Cpp
  2. Python

2.1 Id field

After issuing a request frame using the I2C bus write operation, the I2C bus master will read the response frame from the I2C-HAT using the I2C bus read operation. Response frame Id will be the same as Request frame Id. Generating a new frame Id for every request frame is recommended, this could be done by simply incrementing the frame Id.

2.2 Command field

Response frame Command will be the same as Request frame Command. Using frame Command and frame Id, the I2C bus master can make sure that the response frame corresponds to his request frame.

Code Description
0x10 Get board name
0x11 Get firmware version
0x12 Get status word
0x13 Reset
0x14 Set Communication Watchdog period
0x15 Get Communication Watchdog period
IRQ  
0x16 Get IRQ Register
0x17 Set IRQ Register
Digital Inputs  
0x20 Get value
0x21 Get channel state
0x22 Get counter
0x23 Reset counter
0x24 Reset all counters
Digital Outputs  
0x30 Set PowerOn value
0x31 Get PowerOn value
0x32 Set Safety value
0x33 Get Safety value
0x34 Set value
0x35 Get value
0x36 Set channel state
0x37 Get channel state

2.3 Data field

Payload data and size depends on Command byte, for some Commands this field is empty.

2.4 CRC

The Modus 16bit CRC is used for data integrity check. CRC is calculated over the Id, Command and Data fields.

CRC implementations:

  1. Cpp
  2. Python

3. Common commands

3.1 Get board name(0x10)

Request Frame

This request frame has no Data field. To send this request frame, the I2C bus master should issue a I2C bus write for 4 bytes(1[Id] + 1[Command] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x80, 0x03, 0x10, 0x00, 0x8C, P

S I2C bus Start
0x80 I2C bus Write at 0x40 address(DI16ac I2C-HAT)
0x03 Frame Id
0x10 Frame Command
0x00, 0x8C Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is a string of 25 characters representing the board name. If the board name length is smaller than 25 the rest of the bytes will pe trailing zeros. To receive this response frame, the I2C bus master should issue a I2C bus read for 29 bytes(1[Id] + 1[Command] + 25[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x81, 0x03, 0x10, 0x44, 0x49, 0x31, 0x36, 0x61, 0x63, 0x20, 0x49, 0x32, 0x43, 0x2D, 0x48, 0x41, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x29, P

S I2C bus Start
0x81 I2C bus Read at 0x40 address(DI16ac I2C-HAT)
0x03 Frame Id, same as Request Frame Id
0x10 Frame Command, same as Request Frame Command
0x44 .. 0x00 Frame Data payload, 25 bytes length, “DI16ac I2C-HAT” with trailing zeros
0x63, 0x29 Frame CRC, LSB first
P I2C bus Stop

3.2 Get firmware version(0x11)

Request Frame

This request frame has no Data field. To send this request frame, the I2C bus master should issue a I2C bus write for 4 bytes(1[Id] + 1[Command] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x80, 0x04, 0x11, 0xC3, 0x7C, P

S I2C bus Start
0x80 I2C bus Write at 0x40 address(DI16ac I2C-HAT)
0x04 Frame Id
0x11 Frame Command
0xC3, 0x7C Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is 3 bytes long representing the firmware verison(major, minor, patch). To receive this response frame, the I2C bus master should issue a I2C bus read for 7 bytes(1[Id] + 1[Command] + 3[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x81, 0x04, 0x11, 0x01, 0x02, 0x00, 0x80, 0x5C, P

S I2C bus Start
0x81 I2C bus Read at 0x40 address(DI16ac I2C-HAT)
0x04 Frame Id, same as Request Frame Id
0x11 Frame Command, same as Request Frame Command
0x01, 0x02, 0x00 Frame Data payload, 3 bytes length, v.1.2.0
0x80, 0x5C Frame CRC, LSB first
P I2C bus Stop

3.3 Get status word(0x12)

Request Frame

This request frame has no Data field. To send this request frame, the I2C bus master should issue a I2C bus write for 4 bytes(1[Id] + 1[Command] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x80, 0x05, 0x12, 0x82, 0xED, P

S I2C bus Start
0x80 I2C bus Write at 0x40 address(DI16ac I2C-HAT)
0x05 Frame Id
0x12 Frame Command
0x82, 0xED Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is 4 bytes long representing the status word.

Status word bits:

  • [0] POR reset, power on reset
  • [1] SW reset, software reset
  • [2] IWDG reset, indepenent watchdog reset, hardware watchdog
  • [3] CWDT expired, communication wathdog timeout
  • [4] DI IRQ Capture Queue full

Reading the status word will reset all bits.

To receive this response frame, the I2C bus master should issue a I2C bus read for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x81, 0x05, 0x12, 0x01, 0x00, 0x00, 0x00, 0xB9, 0xB1, P

S I2C bus Start
0x81 I2C bus Read at 0x40 address(DI16ac I2C-HAT)
0x05 Frame Id, same as Request Frame Id
0x12 Frame Command, same as Request Frame Command
0x01, 0x00, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 value of status word
0xB9, 0xB1 Frame CRC, LSB first
P I2C bus Stop

3.4 Reset(0x13)

Request Frame

This request frame has no Data field. To send this request frame, the I2C bus master should issue a I2C bus write for 4 bytes(1[Id] + 1[Command] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x80, 0x08, 0x13, 0x47, 0xBD, P

S I2C bus Start
0x80 I2C bus Write at 0x40 address(DI16ac I2C-HAT)
0x08 Frame Id
0x13 Frame Command
0x47, 0xBD Frame CRC, LSB first
P I2C bus Stop

Response Frame

No response frame for Reset command.

3.5 Set Communication Watchdog period(0x14)

Request Frame

The Data field of this request frame has a 4 byte length and contains the period value in milliseconds. To send this request frame, the I2C bus master should issue a I2C bus write for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x80, 0x0A, 0x14, 0x88, 0x13, 0x00, 0x00, 0xEA, 0xD7, P

S I2C bus Start
0x80 I2C bus Write at 0x40 address(DI16ac I2C-HAT)
0x0A Frame Id
0x14 Frame Command
0x88, 0x13, 0x00, 0x00 Frame Data payload, 4 byte length, LSB first, uint32 period value, 5000ms in this example
0xEA, 0xD7 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is 4 bytes long representing the Communication Watchdog timeout period in millisec. To receive this response frame, the I2C bus master should issue a I2C bus read for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x81, 0x0A, 0x14, 0x88, 0x13, 0x00, 0x00, 0xEA, 0xD7, P

S I2C bus Start
0x81 I2C bus Read at 0x40 address(DI16ac I2C-HAT)
0x0A Frame Id, same as Request Frame Id
0x14 Frame Command, same as Request Frame Command
0x88, 0x13, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 period value, 5000ms in this example
0xEA, 0xD7 Frame CRC, LSB first
P I2C bus Stop

3.6 Get Communication Watchdog period(0x15)

Request Frame

This request frame has no Data field. To send this request frame, the I2C bus master should issue a I2C bus write for 4 bytes(1[Id] + 1[Command] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x80, 0x0B, 0x15, 0xC7, 0x4F, P

S I2C bus Start
0x80 I2C bus Write at 0x40 address(DI16ac I2C-HAT)
0x0B Frame Id
0x15 Frame Command
0xC7, 0x4F Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is 4 bytes long representing the Communication Watchdog timeout period in millisec. To receive this response frame, the I2C bus master should issue a I2C bus read for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x81, 0x0B, 0x15, 0x88, 0x13, 0x00, 0x00, 0xD6, 0xC6, P

4 IRQ Commands

The IRQ feature was introduced for the DI16ac and DI6acDq6rly boards, starting from hardware rev2.0 and firmware v2.0.0. The board IRQ output signal is connected to a Raspberry Pi pin(selectable between GPIO20, GPIO21, GPIO22 and GPIO23 using solder jumpers, but default is GPIO21. This Raspberry Pi pin should be configured as input with pull-up resistor enabled, so the IRQ feature uses one more Raspberry GPIO pin besides the I2C bus pins. The board will trigger(pull-down) the IRQ pin when a change is detected on the Digital Inputs Channels, this will inform Raspberry PI that a change has occurred and Raspberry PI should read the associated IRQ registers(DI_Status and DI_capture) and/or the Digital Input Channel states using the I2C bus commands to determine what was the condition that generated the IRQ.

Digital Inputs IRQ Registers

Name Address Description
DI_Falling_Edge_Control 0x20 Setting bits in this register will enable Falling Edge IRQ generation for the corresponding Digital Input channels, 1 bit for every channel, bit 0 for channel 0 and so on.
DI_Rising_Edge_Control 0x21 Setting bits in this register will enable Rising Edge IRQ generation for the corresponding Digital Input channels, 1 bit for every channel, bit 0 for channel 0 and so on.
DI_Capture 0x22 This register is the Capture Queue interface. For every detected IRQ a capture value is put in the Capture Queue.

Capture Queue

A new value is put in this queue for every detected IRQ, this value is composed of the DI_Value(all channels states, 16MSb) and IRQ_Flags(all channels interrupt flags 16LSb).

For example, let’s say the board is configured to detect rising edge interrupts on channel 0 and rising and falling edge interrupts on channel 1(DI_Rising_Edge_Control = 0x03, DI_Falling_Edge_Control = 0x02) and the following sequence of events happen:

  1. rising edge is detected on ch0, this will store 0x00010001 in Capture Queue and trigger the IRQ line.
  2. a rising edge is detected on ch1, this will store 0x00030002 in Capture Queue.
  3. falling edge is detected on ch0, this is ignored because the corresponding interrupt was not enabled.
  4. falling edge is detected on ch1, this will store 0x00000002 in Capture Queue.
  5. User reads Capture Register until it’s 0(0 - means Capture Queue it’s empty)
    • First read returns 0x00010001, this means: DI_Value = 0x0001, IRQ_Flags = 0x0001
    • Second read returns 0x00030002, DI_Value = 0x0003, IRQ_Flags = 0x0002
    • Third read returns 0x00000002, DI_Value = 0x0000, IRQ_Flags = 0x0002, IRQ line is released because there are no more events in Capture Queue
    • Fourth read returns 0x00000000, queue is empty, no more IRQ events

You can use IRQ_Flags combined with DI_Value and get the type of event that generated the IRQ/Capture event. You should check every bit from IRQ_Flags and if it’s set check the same bit value in DI_Value to see what kind of edge(1 - rising, 0 - falling) was detected.

Important!!! The IRQ condition is released by:

  • a read of the Digital Input port(all channels)
  • reading all contents of the Capture Queue(multiple reads of the DI_Capture register until a read returns 0, this means the Capture Queue is empty)
  • clearing the Capture Queue(writing 0 to DI_Capture register will dump all contents).

The Capture Queue has a capacity of 127. In case of over fill bit 4 in StatusWord will be set.

4.1 Get IRQ register(0x16)

Request Frame

The request frame Data field has a length of 1 byte, this byte is the IRQ register. To send this request frame, the I2C bus master should issue a I2C bus write for 5 bytes(1[Id] + 1[Command] + 1[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x04, 0x16, 0x21, 0xFE, 0x79, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x04 Frame Id
0x16 Frame Command
0x21 Frame Data, 1 byte length, IRQ register, DI Rising Edge Control
0xFE, 0x79 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field has a length of 5 bytes, first byte is the IRQ register, the remaining 4 bytes are the register value(uint32_t, LSB first). To receive this response frame, the I2C bus master should issue a I2C bus read for 9 bytes(1[Id] + 1[Command] + 5[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x04, 0x16, 0x21, 0x3F, 0x00, 0x00, 0x00, 0xEC, 0x25, P

S I2C bus Start
0xC1 I2C bus Read at 0x60 address(DI6acDQ6rly I2C-HAT)
0x04 Frame Id, same as Request Frame Id
0x16 Frame Command, same as Request Frame Command
0x21, 0x3F, 0x00, 0x00, 0x00 Frame Data payload, 5 bytes length, first byte is the IRQ register, the remaining 4 bytes, LSB first, uint32 register value
0xEC, 0x25 Frame CRC, LSB first
P I2C bus Stop

4.2 Set IRQ register(0x17)

Request Frame

The request frame Data field has a length of 5 bytes, first byte is the IRQ register, the remaining 4 bytes are the register value(uint32_t, LSB first). To send this request frame, the I2C bus master should issue a I2C bus write for 9 bytes(1[Id] + 1[Command] + 5[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x03, 0x17, 0x21, 0x3F, 0x00, 0x00, 0x00, 0x9B, 0x34, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x03 Frame Id, same as Request Frame Id
0x17 Frame Command, same as Request Frame Command
0x21, 0x3F, 0x00, 0x00, 0x00 Frame Data payload, 5 bytes length, first byte is the IRQ register, the remaining 4 bytes, LSB first, uint32 register value
0x9B, 0x34 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field has a length of 5 bytes, first byte is the IRQ register, the remaining 4 bytes are the register value(uint32_t, LSB first). To receive this response frame, the I2C bus master should issue a I2C bus read for 9 bytes(1[Id] + 1[Command] + 5[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x03, 0x17, 0x21, 0x3F, 0x00, 0x00, 0x00, 0x9B, 0x34, P

S I2C bus Start
0xC1 I2C bus Read at 0x60 address(DI6acDQ6rly I2C-HAT)
0x03 Frame Id, same as Request Frame Id
0x17 Frame Command, same as Request Frame Command
0x21, 0x3F, 0x00, 0x00, 0x00 Frame Data payload, 5 bytes length, first byte is the IRQ register, the remaining 4 bytes, LSB first, uint32 register value
0x9B, 0x34 Frame CRC, LSB first
P I2C bus Stop

5. Digital Inputs commands

5.1 Get value(0x20)

Request Frame

This request frame has no Data field. To send this request frame, the I2C bus master should issue a I2C bus write for 4 bytes(1[Id] + 1[Command] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x80, 0x05, 0x20, 0x03, 0x38, P

S I2C bus Start
0x80 I2C bus Write at 0x40 address(DI16ac I2C-HAT)
0x05 Frame Id
0x20 Frame Command
0x03, 0x38 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is a uint32 value containing the Digital Inputs channel states, one channel per bit. To receive this response frame, the I2C bus master should issue a I2C bus read for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x81, 0x05, 0x20, 0x01, 0x00, 0x00, 0x00, 0x80, 0x75, P

S I2C bus Start
0x81 I2C bus Read at 0x40 address(DI16ac I2C-HAT)
0x05 Frame Id, same as Request Frame Id
0x20 Frame Command, same as Request Frame Command
0x01, 0x00, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 value of Digital Inputs, channel 0 is TRUE for this example
0x80, 0x75 Frame CRC, LSB first
P I2C bus Stop

5.2 Get channel state(0x21)

Request Frame

This request frame Data field has a 1 byte length, this byte is the channel index. To send this request frame, the I2C bus master should issue a I2C bus write for 5 bytes(1[Id] + 1[Command] + 1[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x80, 0x0C, 0x21, 0x00, 0xA9, 0x93, P

S I2C bus Start
0x80 I2C bus Write at 0x40 address(DI16ac I2C-HAT)
0x0C Frame Id
0x21 Frame Command
0x00 Frame Data, 1 byte length, channel index
0xA9, 0x93 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field has a length of 2 bytes, first byte is the channel index, the second byte is the channel state. To receive this response frame, the I2C bus master should issue a I2C bus read for 6 bytes(1[Id] + 1[Command] + 2[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0x81, 0x0C, 0x21, 0x00, 0x00, 0x53, 0x7E, P

S I2C bus Start
0x81 I2C bus Read at 0x40 address(DI16ac I2C-HAT)
0x0C Frame Id, same as Request Frame Id
0x21 Frame Command, same as Request Frame Command
0x00, 0x00 Frame Data payload, 2 bytes length, channel index and channel state(1 byte each), channel 0 state is FALSE in this example
0x53, 0x7E Frame CRC, LSB first
P I2C bus Stop

5.3 Get counter(0x22)

Request Frame

This request frame Data field has length of 2 bytes, first byte is the counter channel index, second byte is the counter type(0 - falling edge, 1 - rising edge). To send this request frame, the I2C bus master should issue a I2C bus write for 6 bytes(1[Id] + 1[Command] + 2[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x26, 0x22, 0x00, 0x01, 0x6A, 0xA6, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x26 Frame Id
0x22 Frame Command
0x00, 0x01 Frame Data, 2 byte length, counter channel index and counter type, counter for channel 0 of type rising edge in this example
0x6A, 0xA6 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field has a length of 6 bytes, first byte is the counter channel index, the second byte is the counter type, the last 4 bytes are the counter value(unit32, LSB first). To receive this response frame, the I2C bus master should issue a I2C bus read for 10 bytes(1[Id] + 1[Command] + 6[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x26, 0x22, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0xFD, 0x73, P

S I2C bus Start
0xC1 I2C bus Read at 0x60 address(DI6acDQ6rly I2C-HAT)
0x26 Frame Id, same as Request Frame Id
0x22 Frame Command, same as Request Frame Command
0x00, 0x01, 0x06, 0x00, 0x00, 0x00 Frame Data payload, 6 bytes length, counter channel index and counter type are the first two bytes, the remaining 4 bytes are the counter value, rising edge counter for channel 0 has a value of 6 in this example
0xFD, 0x73 Frame CRC, LSB first
P I2C bus Stop

5.4 Reset counter(0x23)

Request Frame

This request frame Data field has length of 2 bytes, first byte is the counter channel index, second byte is the counter type(0 - falling edge, 1 - rising edge). To send this request frame, the I2C bus master should issue a I2C bus write for 6 bytes(1[Id] + 1[Command] + 2[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x27, 0x23, 0x00, 0x01, 0x3A, 0x9A, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x27 Frame Id
0x23 Frame Command
0x00, 0x01 Frame Data, 2 byte length, counter channel index and counter type, counter for channel 0 of type rising edge in this example
0x3A, 0x9A Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field has a length of 2 bytes, first byte is the counter channel index, the second byte is the counter type. To receive this response frame, the I2C bus master should issue a I2C bus read for 6 bytes(1[Id] + 1[Command] + 2[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x27, 0x23, 0x00, 0x01, 0x3A, 0x9A, P

S I2C bus Start
0xC1 I2C bus Read at 0x60 address(DI6acDQ6rly I2C-HAT)
0x27 Frame Id, same as Request Frame Id
0x23 Frame Command, same as Request Frame Command
0x00, 0x01 Frame Data payload, 6 bytes length, counter channel index and counter type are the first two bytes, rising edge counter for channel 0 was reset
0x3A, 0x9A Frame CRC, LSB first
P I2C bus Stop

5.5 Reset all counters(0x24)

Request Frame

This request frame has no Data field. To send this request frame, the I2C bus master should issue a I2C bus write for 4 bytes(1[Id] + 1[Command] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x28, 0x24, 0x1F, 0xAB, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x28 Frame Id
0x24 Frame Command
0x1F, 0xAB Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame has no Data field, the I2C bus master should issue a I2C bus read for 4 bytes(1[Id] + 1[Command] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x28, 0x24, 0x1F, 0xAB, P

S I2C bus Start
0xC1 I2C bus Read at 0x60 address(DI6acDQ6rly I2C-HAT)
0x28 Frame Id, same as Request Frame Id
0x24 Frame Command, same as Request Frame Command
0x1F, 0xAB Frame CRC, LSB first
P I2C bus Stop

6. Digital Outputs commands

6.1 Set PowerOn value(0x30)

Request Frame

The request frame Data field is a uint32 value containing the PowerOn channel states, one channel per bit. To send this request frame, the I2C bus master should issue a I2C bus write for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x0F, 0x30, 0x03, 0x00, 0x00, 0x00, 0x40, 0xA4, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x0F Frame Id
0x30 Frame Command
0x03, 0x00, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 PowerOn value, channel 0 and 1 are TRUE for this example
0x40, 0xA4 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is a uint32 value containing the PowerOn channel states, one channel per bit. To receive this response frame, the I2C bus master should issue a I2C bus read for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x0F, 0x30, 0x03, 0x00, 0x00, 0x00, 0x40, 0xA4, P

S I2C bus Start
0xC1 I2C bus Read at 0x60 address(DI6acDQ6rly I2C-HAT)
0x0F Frame Id, same as Request Frame Id
0x30 Frame Command, same as Request Frame Command
0x03, 0x00, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 PowerOn value, channel 0 and 1 are TRUE for this example
0x40, 0xA4 Frame CRC, LSB first
P I2C bus Stop

6.2 Get PowerOn value(0x31)

Request Frame

This request frame has no Data field. To send this request frame, the I2C bus master should issue a I2C bus write for 4 bytes(1[Id] + 1[Command] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x10, 0x31, 0xCD, 0xA4, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x10 Frame Id
0x31 Frame Command
0xCD, 0xA4 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is a uint32 value containing the PowerOn channel states, one channel per bit. To receive this response frame, the I2C bus master should issue a I2C bus read for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x10, 0x31, 0x03, 0x00, 0x00, 0x00, 0x7F, 0x0B, P

S I2C bus Start
0xC1 I2C bus Read at 0x60 address(DI6acDQ6rly I2C-HAT)
0x10 Frame Id, same as Request Frame Id
0x31 Frame Command, same as Request Frame Command
0x03, 0x00, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 PowerOn value, channel 0 and 1 are TRUE for this example
0x7F, 0x0B Frame CRC, LSB first
P I2C bus Stop

6.3 Set Safety value(0x32)

Request Frame

The request frame Data field is a uint32 value containing the Safety channel states, one channel per bit. To send this request frame, the I2C bus master should issue a I2C bus write for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x12, 0x32, 0x02, 0x00, 0x00, 0x00, 0x3B, 0x15, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x12 Frame Id
0x32 Frame Command
0x02, 0x00, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 Safety value, channel 1 is TRUE for this example
0x3B, 0x15 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is a uint32 value containing the Safety channel states, one channel per bit. To receive this response frame, the I2C bus master should issue a I2C bus read for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x12, 0x32, 0x02, 0x00, 0x00, 0x00, 0x3B, 0x15, P

S I2C bus Start
0xC1 I2C bus Read at 0x60 address(DI6acDQ6rly I2C-HAT)
0x12 Frame Id, same as Request Frame Id
0x32 Frame Command, same as Request Frame Command
0x02, 0x00, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 Safety value, channel 1 is TRUE for this example
0x3B, 0x15 Frame CRC, LSB first
P I2C bus Stop

6.4 Get Safety value(0x33)

Request Frame

This request frame has no Data field. To send this request frame, the I2C bus master should issue a I2C bus write for 4 bytes(1[Id] + 1[Command] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x13, 0x33, 0x4C, 0x95, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x13 Frame Id
0x33 Frame Command
0x4C, 0x95 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is a uint32 value containing the Safety channel states, one channel per bit. To receive this response frame, the I2C bus master should issue a I2C bus read for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x13, 0x33, 0x03, 0x00, 0x00, 0x00, 0x07, 0x04, P

S I2C bus Start
0xC1 I2C bus Read at 0x60 address(DI6acDQ6rly I2C-HAT)
0x13 Frame Id, same as Request Frame Id
0x33 Frame Command, same as Request Frame Command
0x02, 0x00, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 Safety value, channel 0 and 1 are TRUE for this example
0x07, 0x04 Frame CRC, LSB first
P I2C bus Stop

6.5 Set value(0x34)

Request Frame

The request frame Data field is a uint32 value containing the Digital Outputs channel states, one channel per bit. To send this request frame, the I2C bus master should issue a I2C bus write for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x09, 0x34, 0x01, 0x00, 0x00, 0x00, 0xB0, 0xBA, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x09 Frame Id
0x34 Frame Command
0x01, 0x00, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 Digital Outputs value, channel 0 is TRUE for this example
0xB0, 0xBA Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is a uint32 value containing the Digital Outputs channel states, one channel per bit. To receive this response frame, the I2C bus master should issue a I2C bus read for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x09, 0x34, 0x01, 0x00, 0x00, 0x00, 0xB0, 0xBA, P

S I2C bus Start
0xC1 I2C bus Read at 0x60 address(DI6acDQ6rly I2C-HAT)
0x09 Frame Id, same as Request Frame Id
0x34 Frame Command, same as Request Frame Command
0x01, 0x00, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 Digital Outputs value, channel 0 is TRUE for this example
0xB0, 0xBA Frame CRC, LSB first
P I2C bus Stop

6.6 Get value(0x35)

Request Frame

This request frame has no Data field. To send this request frame, the I2C bus master should issue a I2C bus write for 4 bytes(1[Id] + 1[Command] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x0A, 0x35, 0xC7, 0x07, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x0A Frame Id
0x35 Frame Command
0xC7, 0x07 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field is a uint32 value containing the Digital Outputs channel states, one channel per bit. To receive this response frame, the I2C bus master should issue a I2C bus read for 8 bytes(1[Id] + 1[Command] + 4[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x0A, 0x35, 0x01, 0x00, 0x00, 0x00, 0x8D, 0x49, P

S I2C bus Start
0xC1 I2C bus Read at 0x60 address(DI6acDQ6rly I2C-HAT)
0x0A Frame Id, same as Request Frame Id
0x35 Frame Command, same as Request Frame Command
0x01, 0x00, 0x00, 0x00 Frame Data payload, 4 bytes length, LSB first, uint32 Digital Outputs value, channel 0 is TRUE for this example
0x8D, 0x49 Frame CRC, LSB first
P I2C bus Stop

6.7 Set channel state(0x36)

Request Frame

This request frame Data field length is 2 bytes, first byte is the channel index, the second byte is the channel state. To send this request frame, the I2C bus master should issue a I2C bus write for 6 bytes(1[Id] + 1[Command] + 2[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x0B, 0x36, 0x00, 0x01, 0x23, 0xCE, P

S I2C bus Start
0xC0 I2C bus Write at 0x60 address(DI6acDQ6rly I2C-HAT)
0x0B Frame Id
0x36 Frame Command
0x00, 0x01 Frame Data, 2 bytes length, channel index and channel state(1 byte each), channel 0 is set to TRUE in this example
0x23, 0xCE Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field has a length of 2 bytes, first byte is the channel index, the second byte is the channel state. To receive this response frame, the I2C bus master should issue a I2C bus read for 6 bytes(1[Id] + 1[Command] + 2[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x0B, 0x36, 0x00, 0x01, 0x23, 0xCE, P

S I2C bus Start
0xC1 I2C bus Read at 0x40 address(DI6acDQ6rly I2C-HAT)
0x0B Frame Id, same as Request Frame Id
0x36 Frame Command, same as Request Frame Command
0x00, 0x01 Frame Data payload, 2 bytes length, channel index and channel state(1 byte each), channel 0 state is TRUE in this example
0x23, 0xCE Frame CRC, LSB first
P I2C bus Stop

6.8 Get channel state(0x37)

Request Frame

This request frame Data field has a 1 byte length, this byte is the channel index. To send this request frame, the I2C bus master should issue a I2C bus write for 5 bytes(1[Id] + 1[Command] + 1[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC0, 0x0D, 0x37, 0x00, 0xF6, 0x33, P

S I2C bus Start
0xC0 I2C bus Write at 0x40 address(DI6acDQ6rly I2C-HAT)
0x0D Frame Id
0x37 Frame Command
0x00 Frame Data, 1 byte length, channel index
0xF6, 0x33 Frame CRC, LSB first
P I2C bus Stop

Response Frame

The response frame Data field has a length of 2 bytes, first byte is the channel index, the second byte is the channel state. To receive this response frame, the I2C bus master should issue a I2C bus read for 6 bytes(1[Id] + 1[Command] + 2[Data] + 2[Crc]) at the targeted I2C-HAT address.

I2C bus data: S, 0xC1, 0x0D, 0x37, 0x00, 0x01, 0x72, 0x86, P

S I2C bus Start
0xC1 I2C bus Read at 0x40 address(DI6acDQ6rly I2C-HAT)
0x0D Frame Id, same as Request Frame Id
0x37 Frame Command, same as Request Frame Command
0x00, 0x01 Frame Data payload, 2 bytes length, channel index and channel state(1 byte each), channel 0 state is TRUE in this example
0x72, 0x86 Frame CRC, LSB first
P I2C bus Stop